As telephone switching systems are required to work non-stop, 24 hours a day, they must comprise the most reliable components, arranged in the most efficient manner possible. However, the use of highly reliable components alone is not enough to guarantee that breakdowns will not occur. Various ways of achieving high reliability and maintainability of telecommunication switching systems have been in existence. Among many schemes, the dual synchronous matched scheme (dual plane operation) has proven very successful.
While this scheme is fairly routine in TDM switching, it has not been adapted for message switching or computing except in specialized cases. The following patents provide some examples. U.S. Pat. No. 5,274,633, issued Dec. 28, 1993 to Kato et al describes an ATM dual switch system in which cells identified in the header are sent either to an active or standby switch. A controller at the output selects the correct cells for output transmission. U.S. Pat. No. 5,153,578, issued Oct. 6, 1992 to Izawa et al teaches an apparatus and method for establishing identical data in a dual ATM switch. It is concerned with synchronization between an active and standby switch. Dummy cells are inserted according to a difference in the cell count between the two switches so that a proper synchronization can be effected at the output. U.S. Pat. No. 5,072,440, issued Dec. 10, 1991 to Isono et al describes ATM switches which include dual self-routing switches and conversion modules to select between an active and a standby switch. The patent is specifically directed to a technique of determining whether or not all cells have been discharged from the active switch before an actual switchover. European Patent No. 0 359 352, published on Mar. 21, 1990 (Chopping et al), is directed to a synchronous switch network of dual plane operation. The patent ensures the reliability of the network by "Scissors Crossover", where data streams are distributed to two planes at each stage, e.g. at line termination, switch, and transmission. U.S. Pat. No. 5,285,441, issued Feb. 8, 1994 to Bansal et al, on the other hand, describes a line protection technique in an ATM switch. The technique is concerned with errorless switching between active and standby lines. A controllable amount of time delay is introduced in one of two channels connecting the lines and a switching means in the form of RAM. Leading data is directed into the line with the time delay and lagging data into the other, and errorless switching is conducted after a proper time delay is effected to the leading data.
The present invention addresses difficulties associated with ATM switches which operate in dual switch planes for the purpose of better reliability and maintainability. Specifically, in known dual plane switches even a single fault in one link would bring down the entire plane, even though remaining links from other ports in the same plane may be functioning normally. It is also common that the time delay of cell transmission through each plane is different from each other due to link length, processing time of cells or various other factors. Furthermore, transmission errors may cause infinite delay, that is to say, an identical cell may not appear at all in the other plane. However, it is necessary that the two planes of the prior art system work in close synchrony or within a tolerable range of deviation from a predetermined time delay difference so that cells can be properly aligned between the two planes. Otherwise, cells may be duplicated, wrongly discarded or mis-ordered. The present invention realizes an ATM switch which withstands multiple faults in the system, unless the faults occur in links in both planes between one port and the switch fabric. The switch of the present invention requires no strict synchronization between planes. In particular, the invention utilizes the concept of symmetric and asymmetric traffic, both composed in unit cells so that cells at the destination are correctly gathered even when faults or degradation occurs in links in switch planes.